1. Field of the Invention
The present invention relates to a memory access control circuit of controlling an access operation of a data processing device with respect to a synchronous memory.
2. Description of the Prior Art
With recent improvements in semiconductor process technology, large-scale system circuits have been widely developed. In some large-scale system circuits, a plurality of data processing devices are provided in a single system. Such large-scale system circuits (data processing system) often adopt a unified memory access system in which the data processing devices use a single memory in common. The unified memory access system is typically provided with a memory access control circuit which arbitrates data transfer requests issued from a plurality of data processing devices to a single memory. A memory access control circuit for use in the unified memory access system has been proposed, which limits a data transfer length to a fixed length, divides each data transfer request from a plurality of data processing devices into fixed-length data transfer requests, and arbitrates the divided requests (see, for example, Japanese Patent Unexamined Publication No. 2004-46371).
The unified memory access system often uses an SDRAM (Synchronous DRAM). The SDRAM comprises a column address counter in which a column address is externally supplied and preset, and can readily perform continuous data access by internally incrementing the counter. Such access is called burst access.
In the SDRAM, when another column address is input during burst access, data located at the same row address and the other column address can be accessed.
Note that, if row addresses are changed during continuous access, an operation time of a row address system (e.g., a time required for precharging, etc.) is required in addition to an operation time of a column address system, so that it takes an extra long time to read out data.
In order to eliminate such an extra access time, the SDRAM comprises a plurality of memory blocks (hereinafter referred to as a memory bank, or simply a bank) which can be independently operated. In general, the SDRAM comprises a plurality of memory banks (e.g., a bank A, a bank B, a bank C, and a bank D). These memory banks are repeatedly accessed in sequence, thereby making it possible to achieve efficient data transfer.
FIG. 11 illustrates access timing with which the banks A to D of the SDRAM are repeatedly accessed in sequence. FIG. 11 illustrates an example in which the banks are switched every four words, CL (column address strobe (CAS) latency: the number of memory cycles from when a column address is determined to when read data is determined) is three cycles.
For example, in the SDRAM which operates with this access timing, initially, an active command (Act) is used to select the bank A and provide a row address 0 (Row 0). Thereafter, a read command (Read) is input to designate a column address 0 (Col 0), thereby reading 4-word data A00 to A03 in sequence from the bank A. Thereafter, an active command designating the bank B, and a read command are input, and 4-word data is read from the bank B. Similarly, sequential access is performed for the banks C and D, so that 4-word data is read out from the banks.
Input of an active command (Act), designation of a row address, and designation of a column address by a read command (Read) with respect to the bank B can be issued at some point during the time when the bank A is accessed. Therefore, at some point during the time when a certain bank is accessed, a command is issued in advance with respect to the next bank to be accessed. By accessing the banks A to D in sequence in this manner, it is possible to eliminate a waste access time, resulting in efficient memory access. Further, in the example of FIG. 11, a precharge command (Pre) is input to the banks A and B so as to access Rows 1 of the banks A and B.
Therefore, in the unified memory access system composed of the SDRAM, when continuous data, such as audio data or image data, is stored in the SDRAM, it is possible to perform efficient data transfer. For example, FIG. 12 illustrates that the bank structure of the SDRAM is used to store continuous data, such as image data. In this example, continuous data corresponding to one line of an image is stored in the banks A to D in units of 4 words. Specifically, data 0 to data 3 are stored in the bank A, data 4 to data 7 are stored in the bank B, data 8 to data 11 are stored in the bank C, and data 12 to data 15 are stored in bank D. Data corresponding to the following one line is similarly stored in the banks A to D in units of 4 words.
The data thus stored is controlled by the memory access control circuit. For example, when a read start position is 0 and a transfer size is 16 words, the banks A to D are each accessed once so that data corresponding to one line of an image is efficiently transferred as illustrated in FIG. 13A.
However, in the above-described memory access control circuit, when data is read from some midpoint of a bank, waste data transfer may occur.
For example, as illustrated in FIG. 13B, when a read start position is 4 and a transfer size is 16 words, the banks A to D are each accessed twice in the system in which 4 banks are continuously accessed. In this case, access to the bank A at the time of the first request and access to the banks B to D at the time of the second request are wasteful, resulting in inefficient transfer.
Also, as illustrated in FIG. 13C, when a read start position is 0 and a transfer size is 90 words, the banks A to D are each accessed six times in the system in which 4 banks are continuously accessed. Also, as illustrated in FIG. 13D, when a read start position is 90 and a transfer size is 90 words, the banks A to D are each accessed seven times. Concerning the data transfer of FIGS. 13C and 13D, the data transfer of FIG. 13D has the number of times of access which is larger by one than that of FIG. 13C, no matter that the transfer size is the same 90 words.
As described above, the transfer efficiency of the above-described memory access control circuit of the unified memory access system varies depending on the read start position.
To address such transfer inefficiency, a memory access control circuit has been proposed, which changes the sequence of data to be read from the SDRAM so that memory access is always started from a predetermined bank and ended in another predetermined bank, thereby eliminating waste access (see, for example, Japanese Patent Unexamined Publication No. 2000-251470).
However, in the case of the memory access control circuit which changes the sequence of data to be read out, for a bank which is accessed from some midpoint thereof, data at another column address is combined in the same bank, depending on the read start position, thereby performing data transfer with burst transfer size. Therefore, a column address needs to be input again at some point during the time when data transfer (burst transfer) is performed. Assuming that column addresses are changed at some point during the time when burst transfer is performed, when access to one bank is ended and the next bank is accessed, an invalid period (a period during which data is not output) occurs, resulting in a decrease in data transfer efficiency.
For example, FIG. 14 illustrates timing with which the SDRAM is accessed in a manner such that, when the banks A to D of the SDRAM are accessed in sequence, only column addresses are changed, but not row addresses, when the bank A is being accessed. In this example, when burst access is being performed with respect to Row 1 and Col 0 of the bank A, only the column address is changed to Col 6 while keeping the same bank and the same row address, and access is performed. In this case, another column address is input during burst access, an active command (Act), a read command (Read), and a write command can no longer be input, so that an invalid period occurs between output data of the bank A and output data of the bank B.